1. Field of the Invention
This invention relates to multiprocessor computer systems and more particularly to control of interrupts in multiprocessor computer systems.
2. Description of the Related Art
Many of todays multiprocessor computer systems utilize an interrupt scheme known as the advanced programmable interrupt controller (APIC). The APIC interrupt scheme allows hardware generated interrupts to be distributed to central processing units (CPUs) such that interrupts tend to avoid CPUs that are busy with higher priority tasks and interrupts tend to be assigned to CPUs that are involved in lower priority tasks. Also, the APIC interrupt approach allows CPUs to send interrupts to other CPUs via what is called an interprocessor interrupt (IPI). The APIC register set has become an industry-wide standard in the personal computer industry and is used by a large number of multiprocessing operating systems.
The APIC scheme includes two distinct interrupt units that reside on separate integrated circuits. One unit is called the input/output (I/O) APIC, which typically resides on an integrated circuit coupled to the industry standard architecture (ISA) bus of a personal computer system. The second unit is the local APIC, which typically resides with each CPU either inside the CPU package or linked to the CPU via its host bus interface. Thus, there is one local APIC for each CPU in the system. The I/O APIC includes input pins that are driven by sources of hardware interrupts. The local APIC includes interrupt prioritization logic and methods for sending and receiving interrupts from external sources such as other local APICs or the I/O APIC.
A typical prior art APIC configuration is illustrated in FIG. 1. Each CPU 10, 12, 14, and 16 has a corresponding local APIC 11, 13, 15, and 17. The local APICs are all connected via APIC bus 20. Also attached to APIC bus 20 is I/O APIC 22 which is typically incorporated in an input/output integrated circuit 24.
The APIC bus 20 allows the various local APICs and the I/O APIC to communicate with each other. Thus, interrupts from, e.g., input/output devices received by the I/O APIC can be communicated to various of the local APICs and thus be serviced by one of the processors in the multiprocessor system.
The prior art APIC approach, as illustrated in FIG. 1, has several disadvantages. If the local APIC is on the central processing unit integrated circuit as shown, for example, in FIG. 1, then the cost of providing the local APIC is high in terms of silicon real estate relative to other potential places in the system. On the other hand, if the local APIC is external to the CPU, but on the host bus, then an additional device must be added to the typical PC architecture. In a multiprocessor system, an additional integrated circuit must be included for each CPU in the system. Further, because the APIC bus is serial, there exists a latency from the time that the hardware interrupt is received on the I/O APIC and the time when that interrupt is transmitted to the local APIC via the serial bus. Further, the protocol for the serial bus is complex and difficult to design. Accordingly, it would be desirable to provide a simpler advanced programmable interrupt controller scheme for use in a multiprocessor environment that avoided expending costly CPU silicon area for interrupt controllers and also reduced latency in interrupt service.
Accordingly, it has been discovered to provide a multi-processor computer system in which a first processor accesses a first set of registers using a first plurality of addresses, each of the addresses corresponding to a first register set of a first local interrupt controller. A second processor accesses a second register set of a second local interrupt controller, using the same first plurality of addresses. The method includes determining which of the first and second processors is a source of an access operation using one of the addresses. That address is modified according to the source of the access operation so that the first set of registers is accessed if the first processor is the source and the second registers is accessed when the second set of registers is the source.
In another embodiment of the invention a multi-processor computer system includes at least a first and second processor. The first processor accesses a first set of registers using a first plurality of addresses. A second processor accesses a second set of registers using the first plurality of addresses. A first integrated circuit is coupled to the first and second processors and forms a bridge between the processors and an input/output bus. The first integrated circuit receives access requests for the first and second sets of registers from the first and second processors, respectively. A second integrated circuit, coupled to the input/output bus, includes a first and a second local interrupt controller, the first and second sets of registers being part of the first and second local interrupt controllers respectively. The first integrated circuit, responsive to an access request from one of the first and second processors to one of the first plurality of addresses, outputs information on the input/output bus indicating the address of the register being accessed and which of the first and second processors made the access request.